1. Field of the Invention
The subject invention relates to image sensor circuitry, and more particularly, to pixel cells, e.g. for a sensor array in an imager.
2. Description of Related Art
Many imaging technologies use integrating pixels, which accumulate photocurrent generated in a photo detector, e.g. a photodiode, to charge an integration capacitor. The amount of signal that the pixel can sense before saturation is referred to as well capacity, and is proportional to the physical value of the integration capacitor. The sensitivity of an integrating pixel (or conversion gain) is also related to the capacitance value of the integration capacitor, but is inversely proportional. Generally, it is desired to have both high sensitivity and large well capacity, but these pixel performance parameters are typically in direct competition.
Traditional integrating pixels have addressed this problem by having multiple modes of operation, e.g. one mode for high sensitivity and one mode for large well capacity. This is typically accomplished by using a small integration capacitor for the high sensitivity mode and enabling a switch to connect an additional, larger integration capacitor to activate the large well capacity mode. This switch is generally implemented by a transistor or transistors that are operated in binary ON or OFF modes. Moreover, sensor architectures are generally designed such that all pixels in an array are being controlled homogenously, so all pixels operate only in high sensitivity mode or high capacity mode.
Traditional integrating pixels have limited imaging quality, in part, due to the trade-off between sensitivity and large well capacity. There is a need in the art for integrating pixels with increased imaging quality. The present disclosure provides a solution for this need.